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Digital Electronics

Study 36 Electrical Engineering MCQs with correct answers and explanations.

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11Electrical EngineeringMedium

NAND gates are preferred over others because these________?

Aconsume least electronic power

Bhave lower fabrication area

Ccan be used to make any gate

Dprovide maximum density in a chip

Correct answer

C. can be used to make any gate

Explanation

The correct answer is can be used to make any gate.

12Electrical EngineeringMedium

The binary code of (21.125)10 is________?

A10101.001

B10101.010

C10100.111

D10100.001

Correct answer

A. 10101.001

Explanation

The correct answer is 10101.001.

13Electrical EngineeringMedium

Which type of CPLD packaging can provide maximum number of pins on the package due to small size of the pins?

APGA

BPLCC

CBGA

DQFP

Correct answer

C. BGA

Explanation

The correct answer is BGA.

14Electrical EngineeringMedium

Assuming 8 bits for data, 1 bit for parity, I start bit and 2 stop bits, the number of characters that 1200 BPS communication line can transmit is________?

A12CPS

B120 CPS

C10 CPS

DNone of the above

Correct answer

A. 12CPS

Explanation

The correct answer is 12CPS.

15Electrical EngineeringMedium

Among the logic families, the family which can be used at very high frequency greater than 100 MHz in a 4 bit synchronous counter is________?

ATTLLS

BECL

CCMOS

DTTLAS

Correct answer

B. ECL

Explanation

The correct answer is ECL.

16Electrical EngineeringMedium

Which mechanism allocates the binary value to the states in order to reduce the cost of the combinational circuits?

AState Evaluation

BState Assignment

CState Reduction

DState Minimization

Correct answer

B. State Assignment

Explanation

The correct answer is State Assignment.

17Electrical EngineeringMedium

The universal gate is ________?

ANone of the above

BAND gate

COR gate

DNAND gate

Correct answer

D. NAND gate

Explanation

The correct answer is NAND gate.

18Electrical EngineeringMedium

What would happen, if smaller logic modules are utilized for performing logical functions associated with FPGA? A. Propagation delay will increase B. FPGA area will increase C. Wastage of logic modules will not be prevented D. Number of interconnected paths in device will decrease?

AC & D

BA & D

CB & C

DA & B

Correct answer

D. A & B

Explanation

The correct answer is A & B.

19Electrical EngineeringMedium

In Boolean algebra, the bar sign (-) indicates________?

AAND operation

BOR operation

CNOT operation

DNone of the above

Correct answer

C. NOT operation

Explanation

The correct answer is NOT operation.

20Electrical EngineeringMedium

The only function of NOT gate is to________?

AInvert input signal

BStop signal

CNone of the above

DAct as a universal gate

Correct answer

A. Invert input signal

Explanation

The correct answer is Invert input signal.

11Electrical EngineeringMedium

NAND gates are preferred over others because these________?

Aconsume least electronic power

Bhave lower fabrication area

Ccan be used to make any gate

Dprovide maximum density in a chip

Correct answer

C. can be used to make any gate

Explanation

The correct answer is can be used to make any gate.

12Electrical EngineeringMedium

The binary code of (21.125)10 is________?

A10101.001

B10101.010

C10100.111

D10100.001

Correct answer

A. 10101.001

Explanation

The correct answer is 10101.001.

13Electrical EngineeringMedium

Which type of CPLD packaging can provide maximum number of pins on the package due to small size of the pins?

APGA

BPLCC

CBGA

DQFP

Correct answer

C. BGA

Explanation

The correct answer is BGA.

14Electrical EngineeringMedium

Assuming 8 bits for data, 1 bit for parity, I start bit and 2 stop bits, the number of characters that 1200 BPS communication line can transmit is________?

A12CPS

B120 CPS

C10 CPS

DNone of the above

Correct answer

A. 12CPS

Explanation

The correct answer is 12CPS.

15Electrical EngineeringMedium

Among the logic families, the family which can be used at very high frequency greater than 100 MHz in a 4 bit synchronous counter is________?

ATTLLS

BECL

CCMOS

DTTLAS

Correct answer

B. ECL

Explanation

The correct answer is ECL.

16Electrical EngineeringMedium

Which mechanism allocates the binary value to the states in order to reduce the cost of the combinational circuits?

AState Evaluation

BState Assignment

CState Reduction

DState Minimization

Correct answer

B. State Assignment

Explanation

The correct answer is State Assignment.

17Electrical EngineeringMedium

The universal gate is ________?

ANone of the above

BAND gate

COR gate

DNAND gate

Correct answer

D. NAND gate

Explanation

The correct answer is NAND gate.

18Electrical EngineeringMedium

What would happen, if smaller logic modules are utilized for performing logical functions associated with FPGA? A. Propagation delay will increase B. FPGA area will increase C. Wastage of logic modules will not be prevented D. Number of interconnected paths in device will decrease?

AC & D

BA & D

CB & C

DA & B

Correct answer

D. A & B

Explanation

The correct answer is A & B.

19Electrical EngineeringMedium

In Boolean algebra, the bar sign (-) indicates________?

AAND operation

BOR operation

CNOT operation

DNone of the above

Correct answer

C. NOT operation

Explanation

The correct answer is NOT operation.

20Electrical EngineeringMedium

The only function of NOT gate is to________?

AInvert input signal

BStop signal

CNone of the above

DAct as a universal gate

Correct answer

A. Invert input signal

Explanation

The correct answer is Invert input signal.